A lateral type field effect transistor (hereinafter referred to as FET), which includes source regions and drain regions located at lattice points and a gate electrode network surrounding the source regions and the drain regions, is disclosed by Sakamoto in the article entitled "High-Efficiency Complementary Power MOS PWM Driver LSI with Low-Loss Full-Mode Sensing" IEEE 1922 Custom IC Conference, 25.7.7 to 25.7.4, as a power MOSFET of low ON-resistance. FIGS. 2(a) and (b) show a conventional MOSFET, wherein FIG. 2(b) is a sectional view taken along B--B of FIG. 2(a) and shows an N+ source region 23 and an N+ drain region 24 are formed respectively in a P-type base region 21, which itself is formed with an N- drain region 22 in a surface layer of an N-type substrate 1. A gate electrode 3 is formed in a plane network on the surface between and above each N+ source region 23 and N+ drain region 24 through oxide gate film 41. Under layer Al wiring 51 contacts with the N+ source region 23 in a contact hole 61 disposed through insulative film 42 which covers the electrode 3. Under layer Al wiring 52 contacts with the N+ drain region 24 in a contact hole 62 disposed through the insulative film 42 which covers the electrode 3. The source side wiring 51 extends over the insulative film 42, and as an perspective plan view FIG. 2(a) shows, over the entire plane except the drain side wiring 52 and a gap 7. Upper layer Al wiring 53 contacts with the under layer Al wiring 52 in a through hole 63 disposed right above the contact hole 62 through inter-layer insulation film 43 which covers the under layer Al wiring 51. As FIG. 2(a) shows, the sources and the drains are formed on the lattice points one by the other. FIG. 3 is an expanded view showing an enlarged X portion of FIG. 2, the surface of which is covered with passivation film 44.
In a pMOSFET structure shown in FIGS. 4(a) and 4(b), a P+ source region 25 is formed directly in the surface of the n type substrate, and a P+drain region is formed in a P- drain region formed in advance. In this pMOSFET, the through hole 63 for the drain side upper layer Al wiring 53 is displaced transversely from above the contact hole 62.
The structure shown in FIGS. 2 and 3 facilitates securing the width and the area of the under layer metal wiring 51 in a narrow space and reducing the resistance of the under layer metal wiring 51 since the upper layer wiring 53 contacts with the under layer wiring 52 in the through hole 63 disposed right above the contact hole 62. However, because the under layer metal wiring 52 which extends into the contact hole 62 is deformed as shown in FIG. 3, a part of the insulative layer 42 formed on the under layer wiring 52 is not etched off and left behind where it has been when the through hole 63 is formed. This causes a great increase of the resistance of the through hole. Even if the insulative layer 42 is completely etched off in that part, the through hole 63 becomes deeper than it should be to prevent the upper metal wiring 53 from extending into the through hole 63. In association with this, the resistance of the through hole greatly increases. And, in the worst case, the upper metal wiring 53 and the under metal electrode 52 do not contact with each other, and the device fails to be correctly formed.
In the structure shown in FIG. 4, the through hole 63 is displaced transversely from above the contact hole 62 in the source-drain direction. This displacement narrows the width d of the under layer wiring 51 in the upper portion between the source and the drain. This narrower width causes a resistance increase of the under layer wiring. The narrower width increases current density, if compared at the same device size, and the increased current density causes electro-migration of the metal wiring when large current lows. To solve this problem, the transverse width of the device to the current direction should be increased, which decreases design freedom of the device layout. Even if one wants to shorten device frequency, that is source-drain spacing, the device frequency will be determined according to the design rules of the under metal wiring, the contact hole and the through hole, since the through hole 63 is located in the source-drain direction. In so far as the pattern of the under layer wiring is concerned, though the width d is the most influenced, width in the other direction is also influenced.
In view of the foregoing, an object of the present invention is to provide a lateral type field effect transistor, comprised of source regions and drain regions formed in a surface layer of a semiconductor substrate, which transistor facilitates reducing resistance of under layer wiring connected to the source region by securing width and area of the under layer wiring, increasing design freedom of the device layout and realizing smaller device pitch.